1. Field of the Invention
This invention relates to computer busing systems, and more particularly to a method of and apparatus for improving performance of a device addressed through subtractive decoding.
2. Description of the Related Art
The personal computer industry is an incredibly dynamic and innovative field. Advancements in speed and power tend to be revolutionary rather than evolutionary, and one day's state-of-the-art is the next day's obsolescence. In the early 1980's, an Intel Corporation 8080 microprocessor running at 4 MHz, was considered leading edge; today, that same company's 80486 running at 66 MHz offers hundreds of times the processing power and yet costs no more than that 8080 system.
But the advances in performance and speed have brought attendant problems. One such problem is associated with the bandwidth of the data pathways within the systems using these incredibly fast processors. When a system's processor ran at 4 Mhz transferring data between the processor, memory, and I/O storage subsystems placed few demands on the system data bus, even when that bus was only eight bits, or one byte, wide. With processor clock speeds approaching 100 MHz, even when using 32- and even 642 -bit wide data paths these once lightly traveled buses can approach gridlock.
Thus, microcomputer system designers have sought and developed more sophisticated buses to handle the transfer of these massive amounts of data. With high speed 24-bit color graphics, lightning fast hard disk drives, and multi-megabyte memory configurations, developers have recently turned their attention to adding intermediate buses known as local buses to systems.
In a typical computer system, the processor has a processor bus connected to memory and possibly to a cache subsystem. That processor bus then interfaces with an expansion bus, such as an Extended Industry Standard Architecture (EISA), Industry Standard Architecture (ISA), or Micro Channel bus. In such a system, however, the high processor speeds can be rendered virtually worthless as the system performance is often limited by the speed of the slowest I/O device or by the speed at which the processor can receive and transmit data to and from that device.
To improve data flow and to better utilize the high clock rates of the newer processors, developers turned to the local bus. A local bus resides logically between the processor bus and the expansion bus, connecting to those buses through bridge circuitry. A number of standards have been developed, including VESA's (Video Equipment Standard Association) VL-Bus, Intel Corporation's PCI (Peripheral Component Interconnect), and Apple Computer Company's QuickRing. FIG. 1 shows the typical layout of a PCI based computer system. As can be seen, a processor-cache-memory subsystem, which typically uses a processor bus, connects through a bridge to PCI. Also connected to PCI are audio and video, graphics, I/O, SCSI, and LAN subsystems. Further, an expansion bus chip set forms the bridge circuitry connecting PCI to the standard expansion bus, such as an EISA bus.
In discussing PCI, a few conventions will be observed. A signal name in all capital letters indicates a defined bus signal. For example, CLK and AD[31..00] respectively represent the PCI clock signal and the 32 PCI address-data signals. These signals are physically asserted active high, and their logical negation is indicated by being preceded with an exclamation point (!). For example, when the CLK line is low, and thus CLK is false, !CLK is true. Signals internal to the device according to the invention will be indicated by capitalizing the first letter.
The PCI specification defines some signals as active low following the special signal type definitions of PCI. These signals' physical lines are indicated in their negated state by being followed by a pound (#) sign. For example, when the physical FRAME# and DEVSEL# lines go low, that represents respectively the start of a frame and a device select. The corresponding logical signals are indicated by dropping the pound (#) sign. Thus, when the FRAME# line is physically low, then the logical signal FRAME is true and the logical signal FRAME is false; that is, the PCI bus is currently in a frame, or transaction. Similarly, when the physical DEVSEL# line is low, the logical signal DEVSEL is true and !DEVSEL is false.
These conventions are consistent with the description of PCI found in the Peripheral Component Interconnect (PCI) Revision 1.0 Specification, Jun. 22, 1992, .COPYRGT.1992 INTEL Corp., and the Nov. 6, 1992, Preliminary Draft Addendum, .COPYRGT.1992 PCI Special Interest Group, both of which are incorporated by reference.
Certain lines and signals are provided by the PCI bus that are used in a device according to the invention. The CLK line provides timing for all transactions on PCI and is an input to every PCI device. All other PCI signals are sampled on the rising edge of CLK, and all other timing parameters are defined with respect to this signal's edge. The PCI address and data signals are multiplexed onto the same lines, AD[31..00]. During the first clock of a transaction, AD[31..00] contain a physical byte address (32 bits); it is this address that is of importance to the device according to the invention. During subsequent clocks, AD[31..00] contain data. Bus commands and byte enables are also multiplexed upon the same lines, C/BE#[3..0]. During the address phase of a transaction, C/BE#[3..0] define the bus command, and during a subsequent data phase they carry byte enables. These bus commands are also of importance to a device constructed according to the invention. A cycle frame signal, FRAME#, is driven by the current bus master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue; when FRAME# is deasserted, the transaction is in the final data phase. The device select signal, DEVSEL#, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected.
FIG. 2 generally illustrates the timing of a PCI addressing. Addressing and device selection on PCI is generally performed through a technique known as positive decoding. The current bus master places an address on the address lines AD[31..00] and a control word on the bus command lines C/BE#[3..0] and then asserts the FRAME# line low (FRAME true) to indicate the start of a transaction. Each device then examines the address and bus command lines and determines if the currently asserted address and bus command select that device. If so, the device claims the transaction by asserting the DEVSEL# line low to acknowledge that it is the selected device. This can be done within one, two, or three clock cycles after the bus master asserts the FRAME# line active low to indicate the start of transaction.
As is also apparent in FIG. 2, PCI performs addressing synchronously with the rising edge of the clock signal CLK. It is on the rising edge that the various signals are sampled. When speaking of signal states and signal transitions with respect to PCI, the terms "asserted" and "deasserted" will refer to the state of the signal on the clock edge, and not to signal transitions. This means that the phrase "signal `x` is asserted on clock `y`" is a shortened equivalence for the phrase "signal `x` is driven such that it will be sampled in the asserted state by all bus agents on clock `y`". Further, a signal is considered asserted when it is true. Thus, DEVSEL# is asserted when it is physically low; in such a case, DEVSEL is true.
Under the PCI standard, one PCI device is allowed to use an alternate form of addressing decoding known as subtractive decoding. The subtractive decode device does not positively decode an address, but instead determines whether no other PCI device has positively decoded the address. If no other device asserts DEVSEL# active low within three clock cycles of the start of a frame, then the subtractive decode device claims the transaction by asserting DEVSEL# low (DEVSEL true).
Typically, an expansion bus bridge is the subtractive decode device, as addresses on the expansion bus are usually fragmented. Further, the system usually does not know beforehand which devices at which I/O addresses will be located on the standard expansion bus. Thus, the expansion bus chip set is made the subtractive decode device, as any "unanswered" address will default to that chip set.
But as can be seen from FIG. 2, this entails a delay of three clock cycles for every expansion bus access. Thus, every time the expansion bus chip set is addressed through subtractive decoding, three extra clock cycles are added to the access. This follows from the need to allow positive decode devices to exercise a "first right of refusal" on the access. Because these extra cycles are required on each access, this could rapidly add up to a large overhead.
Thus, it would be desirable to increase the speed of subtractive decode addressing by eliminating these extra clock cycles.